Consider the following processor design characteristics:
I. Register-to-register arithmetic operations only.
II. Fixed-length instruction format. III. Hardwired control unit.
Which of the characteristics above are used in the design of a RISC processor?
Match the following :
Field
P. UDP Header’s Port Number Q. Ethernet MAC Address R. IPv6 Next Header S. TCP Header’s Sequence Number Length in bits I. 48 II. 8 III. 32
IV. 16
Consider the following statements regarding the slow start phase of the TCP congestion control algorithm. Note the cwnd stands for the TCP congestion window and MSS denotes the Maximum Segment Size.
i. The increases by 2 MSS on every successful acknowledgement.
ii. The approximately doubles on every successful acknowledgment. iii. The increases by 1 MSS every round trip time. iv. The approximately doubles every round trip time.
Which one of the following is correct?
The following are some events that occur after a device controller issues an interrupt while process L is under execution.
(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.
Which one of the following is the correct order in which the events above occur?