A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

I₀ : MUL R₂, R₀, R₁ ; R₂R₀ * R₁
I₁ : DIV R₅, R₃, R₄ ; R₅R₃/R₄
I₂ : ADD R₂,R₅, R₂ ; R₂R₅ + R₂
I₃ : SUB R₅, R₂, R₆ ; R₅R₂ – R₆

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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?

I₀ : MUL R₂, R₀, R₁ ; R₂R₀ * R₁
I₁ : DIV R₅, R₃, R₄ ; R₅R₃/R₄
I₂ : ADD R₂,R₅, R₂ ; R₂R₅ + R₂
I₃ : SUB R₅, R₂, R₆ ; R₅R₂ – R₆